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general description the max9209/max9211/max9213/max9215 serialize 21 bits of lvttl/lvcmos parallel input data to three lvds outputs. a parallel rate clock on a fourth lvds output provides timing for deserialization. the max9209/max9211/max9213/max9215 feature programmable dc balance, which allows isolation between the serializer and deserializer using ac-cou- pling. the dc balance circuits on each channel code the data, limiting the imbalance of transmitted ones and zeros to a defined range. the companion max9210/ max9212/max9214/max9216 deserializers decode the data. when dc balance is not programmed, the serial- izers are compatible with non-dc-balanced, 21-bit seri- alizers like the ds90cr215 and ds90cr217. two frequency ranges and two dc-balance default conditions are available for maximum replacement flexi- bility and compatibility with existing non-dc-balanced serializers. the max9209/max9211/max9213/max9215 are avail- able in tssop and space-saving thin qfn packages. applications automotive navigation systems automotive dvd entertainment systems digital copiers laser printers features ? programmable dc-balanced or non-dc-balanced operation ? dc balance allows ac-coupling for ground-shift tolerance ? as low as 8mhz operation ? pin compatible with ds90cr215 and ds90cr217 in non-dc-balanced mode ? integrated 110 (dc-balanced) and 410 (non- dc-balanced) output resistors ? 5v tolerant lvttl/lvcmos data inputs ? pll requires no external components ? up to 1.785gbps throughput ? lvds outputs meet iec 61000-4-2 and iso 10605 requirements ? lvds outputs conform to ansi tia/eia-644 lvds standard ? low-profile 48-lead tssop and space-saving qfn packages ? -40 c to +85 c operating temperature range ? +3.3v supply max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers ________________________________________________________________ maxim integrated products 1 ordering information 19-2828; rev 3; 6/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * future product?ontact factory for availability. ** ep = exposed pad. part temp range pin-package max9209 etm* -40 c to +85 c 48 thin qfn-ep** max9209eum -40 c to +85 c 48 tssop max9209gum -40 c to +105 c 48 tssop max9211 etm* -40 c to +85 c 48 thin qfn-ep** MAX9211EUM* -40 c to +85 c 48 tssop max9213 etm* -40 c to +85 c 48 thin qfn-ep** max9213eum -40 c to +85 c 48 tssop max9215 etm* -40 c to +85 c 48 thin qfn-ep** max9215eum* -40 c to +85 c 48 tssop pin configurations appear at end of data sheet. txin 0 - 20 21 timing control parallel-to- serial converter and dc-balance logic clock generator pll 7x or 9x lvds driver 0 lvds driver 1 lvds driver 2 lvds clk txout0+ txout0- txout1+ txout1- txout2+ txout2- txclk out+ txclk out- dcb/nc txclk in max9209 max9211 max9213 max9215 functional diagram
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, r l = 100 ? 1%, pwrdwn = high, dcb/nc = high or low, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.5v to +4.0v lvds outputs (txout_, txclk out_) to gnd ...-0.5v to +4.0v 5v tolerant lvttl/lvcmos inputs (txin_, txclk in, pwrdwn ) to gnd ..............-0.5v to +6.0v (dcb/nc) to gnd ......................................-0.5v to (v cc + 0.5v) lvds outputs (txout_, txclk out_) short to gnd and differential short .......................continuous continuous power dissipation (t a = +70?) 48-pin tssop (derate 16mw/? above +70?) ....... 1282mw 48-lead qfn (derate 26.3mw/? above +70?) ......2105mw storage temperature range .............................-65? to +150? junction temperature ......................................................+150? esd protection human body model (r d = 1.5k , c s = 100pf) all pins to gnd.............................................................. 2kv iec 61000-4-2 (r d = 330 , c s = 150pf) contact discharge (txout_, txclk out_) to gnd .... 8kv air gap discharge (txout_, txclk out_) to gnd .. 15kv iso 10605 (r d = 2k , c s = 330pf) contact discharge (txout_, txclk out_) to gnd .... 8kv air gap discharge (txout_, txclk out_) to gnd .. 25kv lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units single-ended inputs (txin_, txclk in, pwrdwn , dcb/nc) txin_, txclk in, pwrdwn 2.0 5.5 high-level input voltage v ih dcb/nc 2.0 v cc + 0.3 v low-level input voltage v il -0.3 +0.8 v input current i in v in = hi g h or l ow , p wrdwn = hi g h or l ow -20 +20 ? input clamp voltage v cl i cl = -18ma -0.9 -1.5 v lvds outputs (txout_, txclk out) differential output voltage v od figure 1 250 350 450 mv change in v od between complementary output states v od figure 1 2 25 mv output offset voltage v os figure 1 1.125 1.25 1.375 v change in v os between complementary output states v os figure 1 10 30 mv v out+ or v out- = 0v or v cc, non-dc-balanced mode -10 ?.7 +10 output short-circuit current i os v out+ or v out- = 0v or v cc , dc-balanced mode -15 ?.2 +15 ma v od = 0v, non-dc-balanced mode (note 3) 5.7 10 magnitude of differential output short-circuit current i osd v od = 0v, dc-balanced mode (note 3) 8.2 15 ma 78 110 147 dc-balanced mode -40? to +105? 78 110 150 292 410 547 differential output resistance r o non-dc-balanced mode -40? to +105? 292 410 564 output high-impedance current i oz pwrdwn = low or v cc = 0v, v out+ = 0v or 3.6v, v out- = 0v or 3.6v -0.5 ?.1 +0.5 a
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units 8mhz max9209/max9211 40 54 16mhz max9209/max9211 48 68 34mhz max9209/max9211 71 90 16mhz max9213/max9215 46 64 34mhz max9213/max9215 59 87 dc-balanced mode, worst-case pattern, c l = 5pf, figure 2 66mhz max9213/max9215 94 108 10mhz max9209/max9211 30 39 20mhz max9209/max9211 37 53 33mhz max9209/max9211 49 70 40mhz max9209/max9211 56 75 20mhz max9213/max9215 36 49 33mhz max9213/max9215 45 62 40mhz max9213/max9215 49 70 66mhz max9213/max9215 68 89 worst-case supply current i ccw non-dc-balanced mode, worst-case pattern, c l = 5pf, figure 2 85mhz max9213/max9215 83 100 ma power-down supply current i ccz pwrdwn = low 17 50 ? dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, r l = 100 ? 1%, pwrdwn = high, dcb/nc = high or low, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.) (notes 1, 2)
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 4 _______________________________________________________________________________________ ac electrical characteristics (v cc = +3.0v to +3.6v, r l = 100 ? 1%, c l = 5pf, pwrdwn = high, dcb/nc = high or low, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.) (notes 4, 5) parameter symbol conditions min typ max units max9209/max9211 150 280 400 lvds low-to-high transition time llht figure 3 max9213/max9215 150 260 350 ps max9209/max9211 150 280 400 lvds high-to-low transition time lhlt figure 3 max9213/max9215 150 260 350 ps txclk in transition time tcit figure 4 4 ns 10mhz max9209/max9211 n/7 x tcip - 0.25 n/7 x tcip n/7 x tcip + 0.25 20mhz max9209/max9211 n/7 x tcip - 0.15 n/7 x tcip n/7 x tcip + 0.15 40mhz max9209/max9211 n/7 x tcip - 0.1 n/7 x tcip n/7 x tcip + 0.1 20mhz max9213/max9215 n/7 x tcip - 0.25 n/7 x tcip n/7 x tcip + 0.25 40mhz max9213/max9215 n/7 x tcip - 0.15 n/7 x tcip n/7 x tcip + 0.15 n = 0, 1, 2, 3, 4, 5, 6 non-dc- balanced mode, figure 5 (note 6) 85mhz max9213/max9215 n/7 x tcip - 0.1 n/7 x tcip n/7 x tcip + 0.1 8mhz max9209/max9211 n/9 x tcip - 0.25 n/9 x tcip n/9 x tcip + 0.25 16mhz max9209/max9211 n/9 x tcip - 0.15 n/9 x tcip n/9 x tcip + 0.15 34mhz max9209/max9211 n/9 x tcip - 0.1 n/9 x tcip n/9 x tcip + 0.1 16mhz max9213/max9215 n/9 x tcip - 0.25 n/9 x tcip n/9 x tcip + 0.25 34mhz max9213/max9215 n/9 x tcip - 0.15 n/9 x tcip n/9 x tcip + 0.15 output pulse position tpposn n = 0, 1, 2, 3, 4, 5, 6, 7, 8 dc-balanced mode, figure 6 (note 6) 66mhz max9213/max9215 n/9 x tcip - 0.1 n/9 x tcip n/9 x tcip + 0.1 ns
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers _______________________________________________________________________________________ 5 worst-case pattern and prbs supply current vs. frequency max9209 toc01 frequency (mhz) supply current (ma) 40 30 20 10 40 60 80 100 20 050 worst-case pattern 2 7 - 1 prbs max9209 dc-balanced mode worst-case pattern and prbs supply current vs. frequency max9209 toc02 frequency (mhz) supply current (ma) 50 40 30 20 10 40 60 80 100 20 060 worst-case pattern 2 7 - 1 prbs max9209 non-dc-balanced mode worst-case and prbs supply current vs. frequency max9209 toc03 frequency (mhz) supply current (ma) 75 60 45 30 40 60 80 100 120 20 15 90 worst-case pattern 2 7 - 1 prbs max9213 non-dc-balanced mode typical operating characteristics (v cc = +3.3v, r l = 100 ? 1%, c l = 5pf, pwrdwn = high, t a = +25 c, unless otherwise noted.) ac electrical characteristics (continued) (v cc = +3.0v to +3.6v, r l = 100 ? 1%, c l = 5pf, pwrdwn = high, dcb/nc = high or low, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.) (notes 4, 5) parameter symbol conditions min typ max units txclk in high time tcih figure 7 0.3 x tcip 0.7 x tc ip ns txclk in low time tcil figure 7 0.3 x tcip 0.7 x tc ip ns txin to txclk in setup tstc figure 7 2.2 ns txin to txclk in hold thtc figure 7 0 ns non-dc-balanced mode, figure 8 3.5 4.5 6.0 txclk in to txclk out delay tccd dc-balanced mode, figure 8 4.7 5.9 7.2 ns serializer phase-locked loop set tplls figure 9 32800 x tcip ns serializer power-down delay tpdd figure 10 14 50 ns txclk in cycle-to-cycle jitter (input clock requirement) tjit 2ns magnitude of differential output voltage v od 595mbps data rate, worst-case pattern 250 mv note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground except v od , v od , and v os . note 2: maximum and minimum limits over temperature are guaranteed by design and characterization. devices are production tested at t a = +25?. note 3: guaranteed by design. note 4: tcip is the period of txclk in. note 5: ac parameters are guaranteed by design and characterization, and are not production tested. limits are set at 6 sigma. note 6: pulse position tpposn is characterized using 2 7 - 1 prbs data.
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 6 _______________________________________________________________________________________ max9213 eye diagram?c-balanced mode max9209 toc08 100mv/div 300ps/div 0v differential txclk in = 66mhz ac-coupled using 0.1 f capacitors 2m of cat-5 utp cable 2 7 - 1 prbs pattern 100 termination all-channels switching max9213 eye diagram?on-dc-balanced mode max9209 toc07 100mv/div 300ps/div txclk in = 85mhz dc-coupled 0v differential 10m of cat-5 utp cable all-channels switching 2 7 - 1 prbs pattern 100 termination max9213 eye diagram?c-balanced mode max9209 toc09 100mv/div 300ps/div 0v differential txclk in = 66mhz ac-coupled using 0.1 f capacitors 5m of cat-5 utp cable all-channels switching 2 7 - 1 prbs pattern 100 termination max9213 eye diagram?c-balanced mode max9209 toc10 100mv/div 300ps/div 0v differential txclk in = 66mhz ac-coupled using 0.1 f capacitors 10m of cat-5 utp cable all-channels switching 2 7 - 1 prbs pattern 100 termination worst-case pattern and prbs supply current vs. frequency frequency (mhz) supply current (ma) 60 45 30 40 60 80 100 120 20 15 75 worst-case pattern 2 7 - 1 prbs max9213 dc-balanced mode max9209 toc04 max9213 eye diagram?on-dc-balanced mode max9209 toc05 100mv/div 300ps/div txclk in = 85mhz dc-coupled 2 7 - 1 prbs pattern 100 termination 0v differential all-channels switching 2m of cat-5 utp cable max9213 eye diagram?on-dc-balanced mode max9209 toc06 100mv/div 300ps/div txclk in = 85mhz dc-coupled 2 7 - 1 prbs pattern 100 termination 0v differential all-channels switching 5m of cat-5 utp cable typical operating characteristics (continued) (v cc = +3.3v, r l = 100 ? 1%, c l = 5pf, pwrdwn = high, t a = +25 c, unless otherwise noted.)
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers _______________________________________________________________________________________ 7 pin description pin tssop qfn name function 1, 3, 4, 44, 45, 47, 48, 38, 39, 41, 42, 43, 45, 46 txin0?xin6 5v tolerant lvttl/lvcmos channel 0 data inputs. internally pulled down to gnd. 2, 8, 14, 21 2, 8, 15, 44 v cc digital supply voltage 5, 11, 17, 24, 46 5, 11, 18, 40, 47 gnd ground 6, 7, 9, 10, 12, 13, 15 1, 3, 4, 6, 7, 9, 48 txin7?xin13 5v tolerant lvttl/lvcmos channel 1 data inputs. internally pulled down to gnd. 16, 18, 19, 20, 22, 23, 25 10, 12, 13, 14, 16, 17, 19 txin14?xin20 5v tolerant lvttl/lvcmos channel 2 data inputs. internally pulled down to gnd. 26 20 txclk in 5v tolerant lvttl/lvcmos parallel rate clock input. internally pulled down to gnd. 27 21 pwrdwn 5v tolerant lvttl/lvcmos power-down input. internally pulled down to gnd. outputs are high impedance when pwrdwn = low or open. 28, 30 22, 24 pll gnd pll ground 29 23 pll v cc pll supply voltage 31, 36, 42 25, 30, 36 lvds gnd lvds ground 32 26 txclk out+ noninverting lvds parallel rate clock output 33 27 txclk out- inverting lvds parallel rate clock output 34 28 txout2+ noninverting channel 2 lvds serial data output 35 29 txout2- inverting channel 2 lvds serial data output 37 31 lvds v cc lvds supply voltage 38 32 txout1+ noninverting channel 1 lvds serial data output 39 33 txout1- inverting channel 1 lvds serial data output 40 34 txout0+ noninverting channel 0 lvds serial data output 41 35 txout0- inverting channel 0 lvds serial data output 43 37 dcb/nc lvttl/lvcmos dc-balance programming input: max9209: pulled up to v cc max9211: pulled down to gnd max9213: pulled up to v cc max9215: pulled down to gnd see table 1. ep ep exposed paddle. solder to ground.
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 8 _______________________________________________________________________________________ vos(-) vos(+) vos(-) vod(+) vod(-) vod(-) txout_- or txclk out- txout_+ or txclk out+ vos = |vos(+) - vos(-)| (txout_+) - (txout_-) or (txclk out+) - (txclk out-) vod = |vod(+) - vod(-)| 0v tcip txclk in odd txin even txin txout_+ or txclk out+ c l c l r l txout_- or txclk out- 80% 80% 20% 20% llht lhlt (txout_+) - (txout_-) or (txclk out+) - (txclk out-) figure 2. worst-case test pattern figure 3. lvds output load and transition times figure 1. lvds output dc parameters 90% 10% 90% 10% v ih txclk in v il tcit tcit figure 4. clock transition time waveform
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers _______________________________________________________________________________________ 9 detailed description the max9209/max9211 operate at a parallel clock fre- quency of 8mhz to 34mhz in dc-balanced mode and 10mhz to 40mhz in non-dc-balanced mode. the max9213/max9215 operate at a parallel clock frequen- cy of 16mhz to 66mhz in dc-balanced mode and 20mhz to 85mhz in non-dc-balanced mode. dc-balanced or non-dc-balanced operation is con- trolled by the dcb/nc pin (see table 1). in non-dc- balanced mode, each channel serializes 7 bits every cycle of the parallel clock. in dc-balanced mode, 9 bits are serialized every clock cycle (7 data bits + 2 dc-bal- ance bits). the highest data rate in dc-balanced mode for the max9213 or max9215 is 66mhz x 9 = 594mbps. in non-dc-balanced mode, the maximum data rate is 85mhz x 7 = 595mbps. a bit time is 1 divided by the data rate, for example, 1 / 595mbps = 1.68ns. dc balance through data coding, the dc-balance circuits limit the imbalance of ones and zeros transmitted on each chan- nel. if +1 is assigned to each binary one transmitted and -1 is assigned to each binary zero transmitted, the variation in the running sum of assigned values is called the digital sum variation (dsv). the maximum dsv for the max9209/max9211/max9213/max9215 txin15 txin14 txin20 txin19 txin18 txin17 txin16 txin15 txin14 txin8 txin7 txin13 txin12 txin11 txin10 txin9 txin8 txin7 txin1 txin0 txin6 txin5 txin4 txin3 txin2 txin1 txin0 cycle n - 1 cycle n tppos0 tppos1 tppos2 tppos3 tppos4 tppos5 tppos6 txclk out (differential) txout2 (single ended) txout1 (single ended) txout0 (single ended) figure 5. non-dc-balanced mode lvds output pulse position measurement device dcb/nc operating mode operating frequency (mhz) high or open dc balanced 8 to 34 max9209 low non-dc balanced 10 to 40 high dc balanced 8 to 34 max9211 low or open non-dc balanced 10 to 40 high or open dc balanced 16 to 66 max9213 low non-dc balanced 20 to 85 high dc balanced 16 to 66 max9215 low or open non-dc balanced 20 to 85 table 1. dc-balance programming
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 10 ______________________________________________________________________________________ dca2 dcb2 txin20 txin19 txin18 txin17 txin16 txin15 txin14 dca1 dcb1 txin13 txin12 txin11 txin10 txin9 txin8 txin7 dca0 dcb0 txin6 txin5 txin4 txin3 txin2 txin1 txin0 cycle n - 1 cycle n tppos0 tppos1 tppos2 tppos3 tppos4 tppos5 tppos6 txclk out (differential) txout2 (single ended) txout1 (single ended) txout0 (single ended) dca2 dcb2 dca1 dcb1 dca0 dcb0 tppos7 tppos8 tcip tcih tcil thtc tstc setup 1.5v 1.5v hold 2.0v 1.5v 0.8v txin 0:20 txclk in txclk out+ txclk in tccd txclk out- 1.5v differential 0 figure 6. dc-balanced mode lvds output pulse position measurement figure 7. setup and hold, high and low times figure 8. clock-in to clock-out delay
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers ______________________________________________________________________________________ 11 data channels is 10. at most, 10 more zeros than ones, or 10 more ones than zeros, are transmitted. the maxi- mum dsv for the clock channel is 5. limiting the dsv and choosing the correct coupling capacitors maintain differential signal amplitude and reduce jitter due to droop on ac-coupled links. to obtain dc balance on the data channels, the parallel input data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. two com- plementary bits are appended to each group of 7 paral- lel input data bits to indicate to the max9210/max9212/ max9214/max9216 deserializers whether the data bits are inverted (figure 11). the deserializer restores the original state of the parallel data. the lvds clock signal alternates duty cycles of 4/9 and 5/9, which maintains dc balance. figure 12 shows the non-dc-balanced mode inputs mapped to lvds outputs. ac-coupling benefits bit errors experienced with dc-coupling can be elimi- nated by increasing the receiver common-mode volt- age range by ac-coupling. ac-coupling increases the dca0 dcb1 dca1 dcb2 dca2 cycle n + 1 cycle n cycle n - 1 txin2 txin6 txin3 txin4 txin5 txin9 txin13 txin10 txin11 txin12 txin2 txin3 txin4 dca0 txin5 txin6 dcb0 txin9 txin10 txin11 dca1 txin12 txin13 dcb1 txin16 txin17 txin18 dca2 txin19 txin20 dcb2 txin0 txin1 txin7 txin8 txin14 txin15 txin16 txin20 txin17 txin18 txin19 dcb0 txclk out- txout1 txout0 txout2 txin1 txin8 txin15 txin0 txin7 txin14 txclk out+ figure 11. dc-balanced mode inputs mapped to lvds outputs 2.0v 3.0v high-z differential 0 3.6v v od = 0 v cc txout_, txclk out txclk in pwrdwn tppls figure 9. pll set time txout_, txclk out txclk in pwrdwn high-z 0.8v tpdd figure 10. power-down delay
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 12 ______________________________________________________________________________________ common-mode voltage range of an lvds receiver to nearly the voltage rating of the capacitor. the typical lvds driver output is 350mv centered on an offset volt- age of 1.25v, making single-ended output voltages of 1.425v and 1.075v. an lvds receiver accepts signals from 0v to 2.4v, allowing approximately 1v common- mode difference between the driver and receiver on a dc-coupled link (2.4v - 1.425v = 0.975v and 1.075v - 0v = 1.075v). figure 13 shows the dc-coupled link, non-dc-balanced mode. txin1 txin7 txin8 txin14 txin15 cycle n + 1 cycle n cycle n - 1 txin2 txin6 txin3 txin4 txin5 txin9 txin13 txin10 txin11 txin12 txin0 txin1 txin2 txin6 txin3 txin4 txin5 txin7 txin8 txin9 txin13 txin10 txin11 txin12 txin14 txin15 txin16 txin20 txin17 txin18 txin19 txin0 txin1 txin7 txin8 txin14 txin15 txin16 txin20 txin17 txin18 txin19 txclk out+ txin0 txclk out- txout1 txout0 txout2 figure 12. non-dc-balanced mode inputs mapped to lvds outputs 1:7 7 7 r t = 100 r t = 100 r t = 100 r t = 100 7:1 7:1 1:7 7 7 7:1 1:7 7 7 pll pll max9209 max9211 max9213 max9215 max9210 max9212 max9214 max9216 txout txclk out rxin rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout pwrdwn txclk in txin transmission line r o r o r o r o figure 13. dc-coupled link, non-dc-balanced mode
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers ______________________________________________________________________________________ 13 common-mode voltage differences may be due to ground potential variation or common-mode noise. if there is more than 1v of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. ac-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. a common-mode voltage differ- ence up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. dc-bal- anced coding of the data is required to maintain the dif- ferential signal amplitude and limit jitter on an ac-coupled link. a capacitor in series with each output of the lvds driver is sufficient for ac-coupling. however, two capacitors?ne at the serializer output and one at the deserializer input?rovide protection in case either end of the cable is shorted to a high voltage. 5v tolerant inputs all signal and control inputs except dcb/nc are 5v tol- erant and are internally pulled down to gnd. the dcb/nc pin has a pulldown on max9211/max9215 and a pullup on the max9209/max9213. dcb/nc pin default conditions the max9209/max9211/max9213/max9215 have pro- grammable dc balance/non-dc balance. see table 1 for dcb/nc default settings and operating modes. (7 + 2):1 1:(9 - 2) 7 7 r t = 100 r t = 100 r t = 100 r t = 100 (7 + 2):1 1:(9 - 2) 7 7 (7 + 2):1 1:(9 - 2) 7 7 pll pll max9209 max9211 max9213 max9215 max9210 max9212 max9214 max9216 txout txclk out rxin rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout pwrdwn txclk in txin high-frequency ceramic surface-mount capacitors can also be placed at serializer instead of deserializer. r o r o r o r o figure 14. two capacitors per link, ac-coupled, dc-balanced mode
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 14 ______________________________________________________________________________________ applications information selection of ac-coupling capacitors voltage droop and the dsv of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the lvds receiver termination resistor (r t ), the lvds driver output resistor (r o ), and the series ac-coupling capac- itors (c). the rc time constant for two equal-value series capacitors is (c x (r t + r o )) / 2 (figure 14). the rc time constant for four equal-value series capacitors is (c x (r t + r o )) / 4 (figure 15). r t is required to match the transmission line imped- ance (usually 100 ) and r o is determined by the lvds driver design, with a minimum value of 78 (see the dc electrical characteristics table). this leaves the capaci- tor selection to change the system time constant. in the following example, the capacitor value for a droop of 2% is calculated. jitter due to this droop is then calculated assuming a 1ns transition time: c = -(2 x t b x dsv) / (ln (1 - d) x (r t + r o )) (eq 1) where: c = ac-coupling capacitor (f) t b = bit time (s) dsv = digital sum variation (integer) ln = natural log d = droop (% of signal amplitude) r t = termination resistor ( ) (7 + 2):1 1:(9 - 2) 7 7 r t = 100 r t = 100 r t = 100 r t = 100 (7 + 2):1 1:(9 - 2) 7 7 (7 + 2):1 1:(9 - 2) 7 7 pll pll max9209 max9211 max9213 max9215 max9210 max9212 max9214 max9216 txout txclk out rxin rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout pwrdwn txclk in txin high-frequency ceramic surface-mount capacitors r o r o r o r o figure 15. four capacitors per link, ac-coupled, dc-balanced mode
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers ______________________________________________________________________________________ 15 r o = output resistance ( ) equation 1 is for two series capacitors (figure 14). the bit time (t b ) is the period of the parallel clock divided by 9. the dsv is 10. see equation 3 for four series capaci- tors (figure 15). the capacitor for 2% maximum droop at 8mhz parallel rate clock is: c = -(2 x t b x dsv) / (ln (1 - d) x (r t + r o )) c = -(2 x 13.9ns x 10) / (ln (1 - .02) x (100 + 78 )) c = 0.0773? jitter due to droop is proportional to the droop and transition time: t j = t t x d (eq 2) where: t j = jitter (s) t t = transition time (s) (0% to 100%) d = droop (% of signal amplitude) jitter due to 2% droop and assumed 1ns transition time is: t j = 1ns x 0.02 t j = 20ps the transition time in a real system depends on the fre- quency response of the cable driven by the serializer. the capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. use high-frequency, surface-mount ceramic capacitors. equation 1 altered for four series capacitors (figure 15) is: c = -(4 x t b x dsv) / (ln (1 - d) x (r t + r o )) (eq 3) integrated termination the max9209/max9211/max9213/max9215 have an integrated output termination resistor across each of the four lvds outputs. these resistors damp reflections from induced noise and mismatches between the trans- mission line impedance and termination resistor at the deserializer input. in dc-balanced mode, the differen- tial output resistance is part of the rc time constant. in non-dc-balanced mode, the output termination is increased to 410 (typ) to reduce power. in power- down mode ( pwrdwn = low) or when the power sup- ply is off, the output resistor is switched out and the lvds outputs are high impedance. pwrdwn and power-off driving pwrdwn low stops the pll, switches out the integrated output termination resistors, puts the lvds outputs in high impedance, and reduces supply current to 50? or less. driving pwrdwn high starts the pll lock to the input clock and switches in the output termi- nation resistors. the lvds outputs are not driven until the pll locks. the differential output resistance pulls the outputs together and the lvds outputs are high impedance to ground. if the power supply is turned off, the output resistors are switched out and the lvds out- puts are high impedance. pll lock time the pll lock time is set by an internal counter. the maxi- mum time to lock is 32,800 clock periods. power and clock should be stable to meet the lock-time specifica- tion. when the pll is locking, the lvds outputs are not active and have a differential output resistance of r o . power-supply bypassing there are separate power domains for lvds, pll, and digital circuits. bypass each lvds v cc , pll v cc , and v cc pin with high-frequency surface-mount ceramic 0.1? and 0.001? capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. lvds outputs the lvds outputs are current sources. the voltage swing is proportional to the load impedance. the out- puts are rated for a differential load of 100 ? 1%. cables and connectors interconnect for lvds typically has a differential imped- ance of 100 . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic field cancel- ing effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver. board layout keep the lvttl/lvcmos input and lvds output sig- nals separated to prevent crosstalk. a four-layer pcb with separate layers for power, ground, lvds outputs, and digital signals is recommended.
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 16 ______________________________________________________________________________________ esd protection the max9209/max9211/max9213/max9215 esd toler- ance is rated for iec 61000-4-2, human body model and iso 10605 standards. iec 61000-4-2 and iso 10605 specify esd tolerance for electronic systems. the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 (figure 16). for iec 61000-4-2, the lvds outputs are rated for ?kv contact and ?5kv air discharge. the human body model discharge com- ponents are c s = 100pf and r d = 1.5k (figure 17). for the human body model, all pins are rated for ?kv contact discharge. the iso 10605 discharge compo- nents are c s = 330pf and r d = 2k (figure 18). for iso 10605, the lvds outputs are rated for ?kv con- tact and ?5kv air discharge. c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 50 to 100 r d 330 figure 16. iec 61000-4-2 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m r d 1.5k c s 100pf figure 17. human body esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 50 to 100 r d 2k c s 330pf figure 18. iso 10605 contact discharge esd test circuit
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers ______________________________________________________________________________________ 17 lvds gnd txout0- txout1- txout1+ txout2- txout2+ txclk out- lvds gnd txclk out+ lvds v cc lvds gnd txout0+ txin9 txin10 gnd txin11 txin12 v cc txin13 txin15 txin14 v cc txin8 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 txin19 gnd txin20 pwrdn pll gnd pll v cc pll gnd txin18 v cc txin17 txin16 gnd txin6 txin5 v cc txin4 txin3 txin2 gnd txin1 dcb/nc txin0 txin7 thin qfn max9209 max9211 max9213 max9215 txclk in 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 txin3 txin2 gnd txin1 txin6 txin5 v cc txin4 top view max9209 max9211 max9213 max9215 txin0 dcb/nc lvds gnd txout0- v cc txin8 txin7 gnd txout0+ txout1- txin10 txin9 38 37 36 35 34 33 32 31 30 29 txout1+ lvds v cc lvds gnd txout2- txout2+ txclk out- txclk out+ lvds gnd pll gnd pll v cc 11 12 13 14 15 16 17 18 19 v cc txin12 txin11 gnd txin15 gnd txin14 txin13 txin17 txin16 20 21 txin18 v cc 22 28 27 pll gnd pwrdwn tssop 23 gnd txin19 24 26 25 txclk in txin20 gnd exposed pad pin configurations chip information max9209 transistor count: 9458 max9211 transistor count: 9458 max9213 transistor count: 9458 max9215 transistor count: 9458 process: cmos
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers 18 ______________________________________________________________________________________ 48l tssop.eps notes: 1. dimensions d & e are reference datums and do not include mold flash. 2. mold flash or protrusions not to exceed 0.15mm on d side, and 0.25mm on e side. 3. controlling dimension: millimeters. 4. this part is compliant with jedec specification mo-153, variations, ed (48l), ee (56l). 5. "n" refers to number of leads. 6. the lead tips must lie within a specified zone. this tolerance zone is defined by two parallel planes. one plane is the seating plane, datum (-c-), the other plane is at the specified distance from (-c-) in the direction indicated. 7. marking is for package orientation reference only. 8. number of leads shown are for reference only. section c-c detail a n side view top view c l 1 h e e d b a a2 a1 bottom view c 0.25 ( ) b1 b c1 base metal c end view seating plane see detail a parting line with plating l package outline, 21-0155 1 1 c 48 & 56l tssop, 6.1mm body aaa 23 a marking package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers ______________________________________________________________________________________ 19 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 32, 44, 48l qfn .eps e l e l a1 a a2 e/ 2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k package outline 21-0144 2 1 f 32, 44, 48, 56l thin qfn, 7x7x0.8m m
max9209/max9211/max9213/max9215 programmable dc-balanced 21-bit serializers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) package outline 21-0144 2 2 f 32, 44, 48, 56l thin qfn, 7x7x0.8m m ___________________revision history pages changed at rev 3: 1?, 9, 14, 15, 18, 19, 20

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